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September 2007

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From:
granville rick <[log in to unmask]>
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Miami University HTML authors <[log in to unmask]>
Date:
Sun, 16 Sep 2007 07:22:19 +0000
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The main challenge in 3-D IC design is performance-weakening heat dissipation, which is already a problem in 2-D chips, as any Stanford students who have written a term paper with their laptops on their laps know. The multi-layer design of 3-D ICs exacerbates the problem, and Mechanical Engineering Professors Ken Goodson and Tom Kenney have been working on flowing fluid through microchannels incorporated in the chips to conduct the heat away.
All this from pencil lead: "graphite is a very old material, but take a tiny tube of graphite and it has totally different properties, says Dai. "That's what nanotech is all about."
Just this April, a large cross-departmental group of Stanford faculty was awarded a multi-million dollar grant to take up such challenges and develop new devices and technology for use in 3-D ICs. Chidsey, for instance, is one of the researchers involved in integrating nanowire transistors into 3-D circuits, which requires being able to position nanowires reliably and accurately. With the development of 3-D ICs, you can expect all-in-one MP3 player-telephone-digital camera-PDA devices the size of Star Trek communicators to hit the shelves at Fry's within this decade.

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